A universal test bench for visible CMOS imagers

Visible CMOS imagers can now be subjected to a complete battery of tests—for sensitivity, dynamics, dark current, noise, conversion factor, quantum yield, linearity, resolution, and remanence—on a new test bench developed by scientists at Leti. The new test bench, which also displays the generated images in real time, will round out the current electrical testing capabilities on unit structures.
The researchers combined a FPGA-based digital operating system with an analog signal conditioning card and a pulsed LED system—all orchestrated by a LabVIEW test sequencer. The test bench was validated on a 3.3 million pixel component and will be used to characterize new generations of imagers.
 

Contact: nicolas.billon.pierron@cea.fr

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