Cryo-CMOS electronics: Thermal and strain effects in FDSOI MOSFETs down to very low temperature

In the context of the development of the cryo-electronics, i.e. the extension of operation of digital or analog electronics to cryogenic temperatures, down to a few tens of mK, in particular for quantum applications, the aim of the post-doctoral project is to continue the effort of modeling and characterization of the FDSOI technology at low temperature (4K and below).

We will focus more particularly on the study of thermal effects in various FDSOI transistor architectures (e.g. planar, nanowires/nanoribbon, 3D Coolcube), integrating in particular a strained channel for NMOS and PMOS. The goal is to be able, from electrical characterizations, to achieve the understanding and modeling of these effects down to very low temperatures, and thus to further improve a compact model for FDSOI CMOS technology valid down to 4K, which is currently under development.

One of the direct industrial applications of this work will be the transfer of this model to STMicroelectronics (in the framework of the IRT Nanolelectronics). This work will also be done in collaboration with the IRIG, for the experimental aspect, in connection with the various teams of the transversal project “quantum computing” at Leti.

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