Deep investigation of GaN/dielectrics gate stack through ab-initio simulations (DFT)

MOS-HEMT devices have erased a lot of interest in the state of art and specifically for compact and high power density applications. Thanks to the presence of a high bi-dimensional gas electron (2deg) at the AlGaN/GaN heterojunction and the very promising GaN thermal resistance and high mobility, these transistors are capable of supporting high currents densities. The MOS-HEMT Gate stack (GaN/dielectrics), one the most crucial technology development, defines the threshold voltage (Vth) and the stability under stress condition (DVth) of these devices. NORMALLY-OFF (Vth>0) and reliable transistors (DVth=0) are highly demanded and desired in systems applications, but unfortunately MOS-HEMT transistors suffers of both fermi pinning (Vth=0) and uncontrolled Vth dynamic under blocking stress. Therefore, ab-intio simulations, based on density functional theory (DFT), will be performed using surface characterization data such as AFM, HRTEM, EDX, HAXPES, XRR and TOF-SIM which gives access to the chemical composition in the near-surface region of the GaN/dielectric stack. These simulations will allow simultaneously to access to the macroscopic properties of the near-interface volume (Ec,Ef..) and also to its interface state and trapping density distribution in the GaN and dielectric volume fundamental for the pinning and dynamic Vth behaviors comprehension. Correlation between simulations and experimental results will also be carried out during this study.

Facebook

Twitter