Management of Spectre and Meltdown information leaks in a RISC V application processor

Since 2018 and the announcement of the Spectre and Meltdow vulnerabilities, the hard-won performance gains of desktop and server processors over the past few decades have been called into question. These vulnerabilities effectively exploit the speculative and out of order execution found in all modern processors to gain in the number of instructions performed per clock cycle. These types of execution open the door to transient microarchitectural changes that can be disclosed due to shared resources within the pipeline and caches and the presence of covert channels that allow for the extraction of leaked data. The latter can be cache memories but also other internal buffers.

The objectives of the thesis will be to understand these mechanisms through the implementation of attacks and leakage evaluation systems via for example the mutual information computation.

Then, for each leak and each microarchitecture (branch prediction, prefetcher, TLB, Load Store unit, execution stage, caches,…), the approach with the least performance penalties will have to be found. An implementation of these countermeasures is planned on the open source processor NaxRiscV 64 bits and Out of Order written in the SpinalHDL language that allows to host and test them with a great modularity.

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