Neural Architecture Search for Binary Neural Networks on In-Memory Computing

Edge Artificial Intelligence and low-level Computer Vision is now massively deployed at the near-sensor level in order to further extend the capabilities of smart embedded imaging systems. This near-sensor intelligence typically allows 1000x gains by capping data transmission, thus improving energy efficiency. The In-Memory Computing (IMC) paradigm offers the opportunity to optimize processing architectures thanks to binarized neural networks (weights and activations on 1 bit). Indeed, the use of a reduced arithmetic involving binary operands (0/1, -1/+1, -1/0/+1) has the advantage of being able to exploit the IMC hardware at its best by combining massively parallelized logic functions followed by thresholdings as “requantized binary scalar products”. ASICs developed at CEA relying on this type of algorithm/architecture co-design enable an energy gain of several orders of magnitude (x100). In that context, this PhD thesis, aims at developing an innovative programming model (with its µ-compiler and a virtual machine) dedicated to this kind of hardware architecture, allowing reconfigurations of the neural network, according to specific application needs. To take advantage of the parallelization of the computations, limiting the memory access costs, the µ-compiler will optimize the sequencing of the commands so as the distribution of the computations with respect to the memories available on the hardware target. In addition, the execution complexity estimated by the virtual machine will feed a Neural Architecture Search (NAS) algorithm. This NAS will then aim at identifying the admissible neural network topology offering the best performance versus consumption trade-off. This way, the versatility of future AI accelerators will be increased in order to path the way to a wider range of inference-based applications.

The thesis work will be partitioned as follow:

– Sate-of the-art study and familiarization with the concepts of binarized neural networks in the context of image processing.

– Handling the analysis tools allowing the automatic generation of NN-related computational graphs.

– Identification of possible data organizations and computing adapted to the existing IMC hardware.

– Programming of the dedicated µ-compiler with its associated Hardware simulator (virtual machine).

– Integration, tuning and exploration of NAS tools with outputs provided by the virtual machine.

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