Characterization and reliability of RF switches, study of the substrate impact on performance.

Context:
Incoming 5G imposes new challenges on RF devices performance such as operating at millimeter-wave frequencies and harsh constraints on linearity to avoid spectral pollution in the adjacent carriers. The best way to efficiently reduce the level of harmonics is to boost the resistivity of the semiconductor beneath the buried oxide. In SOI (Silicon on Insulator) technologies, parasitic charges remain under the BOX (buried oxide) and will be coupled with the RF signal flowing in the channel, thus increasing the second and third harmonic level. Different substrates technologies are available nowadays such as high resistivity and trap-rich making SOI a promising solution for high linearity devices and systems. In an RF Front-End-module (FEM), switch linearity has become a main parameter to ensure an acceptable signal purity. Furthermore, switch reliability is critical for rugged operation as it is the last element of a TX FEM before the antenna and a lot of power is flowing in  the device.

Expected work :
The intern will have in charge the characterization of RF switches and study the impact of both trap-rich and high resistivity substrates on switch performance. He/She will measure series and shunt elemental structures using the linearity setup in LETI at 1GHz and 28GHz to cover standard GSM and 5G application and use an S-parameter test bench to measure their Ron-Coff figure of merit. RF stresses will then be conducted in order to evaluate the degradation of linearity and Ron-Coff under large signal operation. A reliability model will then be constructed from these results, supported by simulation and DC stresses on single devices.
 
If you are interested by the internship, please send your CV and a motivation letter to jose.lugo@cea.fr

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